VLSI design flow is
considered to be the sequence of steps/processes involved in the creation of
Integrated Circuit. Digital flow for analog and digital flow is different when
compared to ASIC.
About
digital IC Design-flow
It is regarded to be a semi-custom
standardized cell-based ASIC design flow that is followed by most designs. The
digital design based fundamental building blocks are combinational logic gates
(AND, NOT, OR, OR-AND-INVERT, AND-OR-INVERT, adders, multiplexers), special
cells (filler cells, delay cells, tie cells) and sequential cells (latches,
Scan flip-flops, Flip-flops) are all custom designed similar to analog design,
characterized, verified and used for larger circuit design. The pre-verified
and pre-designed cell library is known as Standard Cell Library. The leading vlsi coaching centres in Bangalore can help the students to understand all
about VLSI design flow.
Know the steps
involved
- Design specification: IC specification can be given by customer to the company or the latter can design unique IC for them that are likely to be marketed later.
- Architectural design: Design specification is derived by the design architect. Also are derived detailed specifications from top level specifications for reach sub-blocks.
- RTIL design: Partitioned design is provided to RTL design team who design the sub-blocks using HDL like SystemVerilog/Verilog. The entire design gets modeled at higher abstraction level using mixed modeling style.
- Functional Verification: With RTL design, it happens in parallel, where there is developed verification environment by the verification team using HVL like SystemVerilog.
- Logic Synthesis: It is RTL code conversion to gate-level netlist. Once verified, RTL design code is to be functional and bug free according to requirement. The logic-synthesizer CAD tool then coverts code to list of standard cells, ports. Interconnections and pins.
- Design-for-test: Certain changes are made to obtain netlist from synthesis tool to aid later when applying tests for hardware verification.
- Logical Equivalency Checking: There is verified derived RTL code and gate-level netlist.
- Pre-layout Static-Timing Analysis: After verification of functionality, design operation at required speed to be verified thoroughly.
- Power and Floor planning: Floor planning determines required area of chip die, core die within die to permit placement of synthesized design, blockage area where cell is not to be placed, etc. For power planning, routing of power (GND & VDD) to the design is determined.
- Placement: Actual standard cell location to be placed within die’s core is is determined.
- Clock Tree Synthesis: To ensure active edge of clock signal is able to reach every flip-flop simultaneously within the design.
- Global routing: It determines paths by which cells are to connect on 2D plane.
- Detailed routing: It determines exact path interconnections take via 3D space through different metal layers.
- RC Extraction & Physical verification: There is checking of routed and placed design for presence of design rule violations, Schematic vs. Layout mismatches, XOC check, electrical rule violations, Antenna check, etc.
- Post Layout static-timing analysis
- GDSII generation
- Post Silicon Validation & Testing
